A common method for testing high resolution ADCs employs a histogram whereby an input stimulus is applied to the ADC and the resultant converted digital data output is recorded in bins relating to each voltage level applied at the input. The input is designed so that it has a known probability density function (PDF) of expected output converted values. The simplest such stimulus is a ramp which creates the same number of outputs for each code if the converter is perfectly linear, although any stimulus with equal probability of producing any given output code is also acceptable. The ramp may be repeated so the impact of noise is minimised and the number of ‘hits’ for a given code is increased. Any specification errors such as differential non-linearity (DNL) look like a change in the bin width, allowing it to catch more than its fair share of hits. This number of hits can subsequently be processed to extract a measure of the specification error, e.g. the DNL.
FIG. 1 illustrates a standard approach in off-chip automatic test equipment to test highly linear ADCs using the histogram method. A ramp of good linearity is created, which covers a small sub-range of the ADC. The ramp is placed on a series of increasing pedestal voltages. Provided the shape of the ramp is constant and unchanged when given each pedestal voltage, appropriate ‘knitting together’ of the series of sub-ranges can synthesis an equivalent full range PDF ADC response. As shown in FIG. 1, the effective linearity can be improved by a number of bits relating to the number of pedestals.
Whilst off-chip techniques for testing are useful, there is a drive towards having an on-chip solution. However, a problem with integrating a test device to implement the histogram method on-chip is that the PDF of the input signal must be precise and known. Typically, a ramp is used as it has a flat PDF, however for anything beyond 11 or 12 bit ADCs the ramp's own linearity is a limiting factor. Another problem is that a bin is required for each code giving 4000 bins for a 12 bit ADC and 64000 for a 16 bit. If these were all needed at the same instance too much silicon real estate would be required to allow a built in-self test.
U.S. Pat. No. 4,897,650 describes an integrated ADC histogram test method whereby the hardware is sequentially reconfigured to allow a histogram to be created in a segmented fashion one code at a time. The contents of each bin relate to the ‘code widths’. After each bin is filled, the resources (two counters and a comparator) are released and made available for a following code.
U.S. Pat. No. 6,642,870 describes a similar method to test ADCs integrated on-chip using the histogram method but with sequential processing of bins to extract at least a functional characteristic of the converter, before releasing the resources for the next group of codes. In this case, instead of requiring many bins to accumulate a full histogram and carrying out sequential processing on a subset, the histogram bins are always reused by processing to determine at least a functional characteristic of the converter for each group of bins before moving onto the next group.
For high resolution converters a problem with the method of U.S. Pat. No. 6,642,870 is that it assumes each bin range is equal, but in practise, this is not the case, which can lead to errors. Hence, for example the performance can degrade as the supply rails are approached causing the ADC to suffer an INL error. Another problem not addressed by U.S. Pat. No. 4,897,650 or U.S. Pat. No. 6,642,870 is how to create an input signal which has sufficient integrity to test modern ADCs and has linearity requirements of 16 bits and beyond.
Despite the desirability of on-chip testing, including a test circuit on an ADC can add to the design complexity and size, which is a disadvantage. This is particularly true where the entire solution must be created in a relatively small area of on-chip silicon and a ramp method is used as the test stimulus. The rate of rise of the ramp is often too fast to give sufficient ‘granularity’ targeting sufficient hits per code because the input signal ramps too fast past each voltage corresponding to a code.